Many currently available processors are configured to perform floating-point arithmetic such as, for example, division and squareroot, in compliance with the IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754-1985). which is incorporated herein by reference. In these processors, the exponent of the result of the operation is generally calculated after the mantissa computation is completed. Thus, the calculation of the resulting exponent is in the critical path of the division and squareroot operations.
Moreover, the mantissa computation can require twenty or more processor clock cycles to complete when using double precision. Thus, calculation of the resultant exponent has a relatively long latency. As is well known, the resultant exponent can then be checked for overflow and underflow exceptions, which are defined in the aforementioned IEEE standard.
The relatively long latency of the resulting exponent calculation can become problematic in the so-called superscalar type of processor. In particular, because superscalar processors may concurrently execute two or more instructions, an instruction may complete after a later-occurring instruction, which can result in an error. For example, an error may occur if the later-occurring instruction overwrites a register before a prior floating-point division instruction completes and an overflow or underflow exception occurs for a prior floating-point division operation. The error occurs because when an exception occurs during an instruction (i.e., the trapping instruction), the processor is required to abort all subsequent instructions and request a trap. After the trap-handler completes execution of the trapping instruction, the processor is restarted at the instruction immediately after the trapping instruction. Of course, the completion of a subsequent instruction that overwrites a register before the exception is handled by the trap-handler can cause an error in the program execution.
Because the resultant exponent is not calculated until late in the instruction execution, a conventional solution to this problem is to make a prediction (before the next subsequent instruction completes) of whether an overflow or underflow exception will occur. In this conventional scheme, a pessimistic prediction is performed to ensure that no overflow or underflow exceptions will be missed by the trap-handler. Of course, pessimistic prediction will result in unnecessary traps, which decreases the performance of the processor. Thus, there is a need for a processor capable of early and exact calculation of the resultant exponent, which both increases performance and allows exact prediction of overflow and underflow.